🔌 第24课：I2C接口

// I2C主控制器
module i2c_master #(
    parameter CLK_FREQ = 50000000,
    parameter I2C_CLK  = 100000    // 100kHz标准模式
)(
    input  wire        clk,
    input  wire        rst,
    // 命令接口
    input  wire [7:0]  dev_addr,    // 设备地址(7位+R/W)
    input  wire [7:0]  wr_data,     // 写数据
    input  wire        start,       // 启动传输
    output reg  [7:0]  rd_data,     // 读数据
    output reg         done,        // 传输完成
    output reg         ack_error,   // NACK错误
    // I2C总线
    output reg         scl_o,       // SCL输出
    output reg         sda_o,       // SDA输出
    output reg         sda_oe,      // SDA输出使能(开漏)
    input  wire        sda_i        // SDA输入
);
    // 时钟分频: 50MHz → 100kHz → 每半周期250个时钟
    localparam HALF = CLK_FREQ / (2 * I2C_CLK);
    reg [15:0] clk_div;

    always @(posedge clk) begin
        if (rst) clk_div <= 0;
        else clk_div <= (clk_div >= HALF - 1) ? 0 : clk_div + 1;
    end

    wire clk_tick = (clk_div == HALF - 1);

    // 状态机
    localparam IDLE=0, START=1, ADDR=2, ACK0=3,
               WR_DATA=4, ACK1=5, RD_DATA=6, ACK2=7, STOP=8;
    reg [3:0] state;
    reg [2:0] bit_cnt;
    reg [7:0] shift_reg;

    always @(posedge clk) begin
        if (rst) begin
            state <= IDLE; scl_o <= 1; sda_o <= 1;
            sda_oe <= 0; done <= 0; ack_error <= 0;
            bit_cnt <= 0; shift_reg <= 0;
        end else if (clk_tick) begin
            done <= 0;
            case(state)
                IDLE: begin
                    scl_o <= 1; sda_o <= 1; sda_oe <= 0;
                    if (start) begin
                        state <= START;
                        shift_reg <= dev_addr;
                        bit_cnt <= 0;
                    end
                end
                START: begin // SCL=1时SDA↓
                    sda_o <= 0; sda_oe <= 1;
                    state <= ADDR; bit_cnt <= 0;
                end
                ADDR: begin
                    scl_o <= 0; // SCL低时设置SDA
                    sda_o <= shift_reg[7]; sda_oe <= 1;
                    shift_reg <= {shift_reg[6:0], 1'b0};
                    scl_o <= 1; // SCL高时从设备采样
                    if (bit_cnt >= 7) state <= ACK0;
                    else bit_cnt <= bit_cnt + 1;
                end
                ACK0: begin
                    scl_o <= 1; sda_oe <= 0; // 释放SDA
                    if (sda_i) ack_error <= 1; // NACK
                    state <= WR_DATA; bit_cnt <= 0;
                    shift_reg <= wr_data;
                end
                WR_DATA: begin
                    scl_o <= 0;
                    sda_o <= shift_reg[7]; sda_oe <= 1;
                    shift_reg <= {shift_reg[6:0], 1'b0};
                    scl_o <= 1;
                    if (bit_cnt >= 7) state <= ACK1;
                    else bit_cnt <= bit_cnt + 1;
                end
                ACK1: begin
                    scl_o <= 1; sda_oe <= 0;
                    state <= STOP;
                end
                STOP: begin // SCL=1时SDA↑
                    scl_o <= 0; sda_o <= 0; sda_oe <= 1;
                    scl_o <= 1; sda_o <= 1;
                    state <= IDLE; done <= 1;
                end
                default: state <= IDLE;
            endcase
        end
    end
endmodule

module i2c_master_tb;
    logic clk=0, rst=1;
    logic [7:0] dev_addr, wr_data;
    logic start, done, ack_error;
    logic scl_o, sda_o, sda_oe;
    logic sda_i;

    assign sda_i = sda_oe ? 1'bz : 1'b1; // 简化: 从设备总是ACK
    i2c_master #(.CLK_FREQ(1000), .I2C_CLK(100)) uut(.*);
    always #5 clk = ~clk;

    initial begin
        rst=1; #50; rst=0;
        $display("--- I2C Master测试 ---");
        dev_addr = 8'hA0; // EEPROM地址+写
        wr_data  = 8'h55;
        start = 1; #10; start = 0;
        wait(done);
        $display("  写入0x55到0xA0 %s", ack_error?"NACK":"ACK ✓");
        $display("I2C Master测试完成 ✓");
        #100; $finish;
    end
endmodule