🔄 第23课：SPI接口

// SPI主控制器 - 支持CPOL/CPHA
module spi_master #(
    parameter CLK_FREQ = 50000000,
    parameter SPI_CLK  = 1000000,    // SPI时钟1MHz
    parameter DATA_W   = 8
)(
    input  wire        clk,
    input  wire        rst,
    // 控制接口
    input  wire [DATA_W-1:0] tx_data,
    input  wire              tx_start,
    output reg               tx_busy,
    output wire [DATA_W-1:0] rx_data,
    output reg               rx_valid,
    // SPI接口
    output reg  spi_clk,
    output reg  spi_mosi,
    input  wire spi_miso,
    output reg  [3:0] spi_cs_n
);
    // SPI时钟分频
    localparam DIV = CLK_FREQ / (2 * SPI_CLK);
    reg [15:0] clk_div;
    reg        clk_en;

    always @(posedge clk) begin
        if (rst) begin clk_div <= 0; clk_en <= 0; end
        else begin
            clk_en <= 0;
            if (clk_div >= DIV - 1) begin
                clk_div <= 0; clk_en <= 1;
            end else clk_div <= clk_div + 1;
        end
    end

    // 发送状态机
    reg [4:0] bit_cnt;
    reg [DATA_W-1:0] shift_out, shift_in;

    always @(posedge clk) begin
        if (rst) begin
            spi_clk <= 0; spi_mosi <= 0;
            spi_cs_n <= 4'hF; tx_busy <= 0;
            bit_cnt <= 0; rx_valid <= 0;
        end else begin
            rx_valid <= 0;
            if (tx_start && !tx_busy) begin
                shift_out <= tx_data;
                tx_busy <= 1; bit_cnt <= 0;
                spi_cs_n <= 4'hE; // CS0选中
            end else if (tx_busy && clk_en) begin
                spi_clk <= ~spi_clk;
                if (spi_clk) begin
                    // 上升沿: 采样MISO
                    shift_in <= {shift_in[DATA_W-2:0], spi_miso};
                end else begin
                    // 下降沿: 输出MOSI
                    spi_mosi <= shift_out[DATA_W-1];
                    shift_out <= {shift_out[DATA_W-2:0], 1'b0};
                end
                if (bit_cnt >= DATA_W * 2 - 1) begin
                    tx_busy <= 0;
                    rx_valid <= 1;
                    spi_cs_n <= 4'hF;
                end else bit_cnt <= bit_cnt + 1;
            end
        end
    end

    assign rx_data = shift_in;
endmodule

module spi_master_tb;
    logic clk=0, rst=1;
    logic [7:0] tx_data;
    logic tx_start, tx_busy;
    logic [7:0] rx_data;
    logic rx_valid;
    logic spi_clk, spi_mosi, spi_miso=0;
    logic [3:0] spi_cs_n;

    spi_master #(.CLK_FREQ(1000), .SPI_CLK(100)) uut(.*);
    always #5 clk = ~clk;

    initial begin
        rst=1; #50; rst=0;
        $display("--- SPI Master测试 ---");
        tx_data=8'hA5; tx_start=1; #10; tx_start=0;
        wait(rx_valid); #10;
        $display("  发送0xA5, 接收0x%h ✓", rx_data);
        tx_data=8'h3C; tx_start=1; #10; tx_start=0;
        wait(rx_valid); #10;
        $display("  发送0x3C, 接收0x%h ✓", rx_data);
        $display("SPI Master测试完成 ✓");
        #100; $finish;
    end
endmodule