第12课：LDPC码

LDPC码：逼近Shannon极限

LDPC(Low-Density Parity-Check)码由Gallager于1963年提出，沉寂30年后被重新发现，现已成为5G NR数据信道的核心编码。LDPC码的校验矩阵非常稀疏(低密度)，支持高效的迭代解码。

LDPC码的Tanner图与消息传递

🔧 Verilog实现

// ldpc_min_sum.v - LDPC Min-Sum解码器
module ldpc_min_sum #(
    parameter Z = 48,
    parameter MAX_ITER = 8,
    parameter DATA_W = 6
)(
    input  wire clk, rst_n,
    input  wire signed [DATA_W-1:0] llr_in [0:Z-1],
    input  wire llr_valid,
    output reg  [0:Z-1] hard_out,
    output reg  dec_valid,
    output reg  iter_count
);
    reg signed [DATA_W-1:0] vn_llr [0:Z-1];
    reg signed [DATA_W-1:0] cn_msg [0:Z-1];
    reg [3:0] iter;
    reg check_pass;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin iter <= 0; dec_valid <= 0; end
        else if (llr_valid && iter < MAX_ITER) begin
            // VN update: vn = llr + sum(cn_msg)
            for (integer i=0; i<Z; i=i+1)
                vn_llr[i] <= llr_in[i] + cn_msg[i];
            // CN update: Min-Sum approximation
            for (integer i=0; i<Z; i=i+1)
                cn_msg[i] <= (vn_llr[i] > 0) ? -vn_llr[i] : vn_llr[i];
            iter <= iter + 1;
            // Hard decision
            for (integer i=0; i<Z; i=i+1)
                hard_out[i] <= vn_llr[i][DATA_W-1];
        end else if (iter == MAX_ITER) dec_valid <= 1;
    end
endmodule

🐍 Python仿真

#!/usr/bin/env python3
import numpy as np
import matplotlib.pyplot as plt
def ldpc_decode_min_sum(llr, H, max_iter=20, alpha=0.75):
    m, n = H.shape
    vn_to_cn = np.zeros((m,n))
    for it in range(max_iter):
        # CN update
        for i in range(m):
            idx = np.where(H[i])[0]
            for j in idx:
                other = [k for k in idx if k != j]
                signs = np.sign(vn_to_cn[i,other]+llr[other])
                mags = np.abs(vn_to_cn[i,other]+llr[other])
                vn_to_cn[i,j] = alpha * np.prod(signs) * np.min(mags+1e-10)
        # VN update and hard decision
        total = llr + np.sum(vn_to_cn, axis=0)
        dec = (total < 0).astype(int)
        if np.all(np.mod(H @ dec, 2) == 0):
            return dec, it+1
    return dec, max_iter
print("LDPC decoder ready")

深入分析与设计考量

本课主题在数字通信系统中扮演关键角色。理解其设计权衡对构建高效通信系统至关重要。在实际工程中，需要在性能、复杂度和资源之间找到最优平衡点。

与其他模块的接口设计

在完整的通信系统中，本课模块需要与上下游模块正确对接。接口设计遵循AXI-Stream协议：tdata(数据)、tvalid(有效)、tready(就绪)、tlast(包结束)。这种握手协议保证了模块间的数据流控制，避免数据丢失。

LDPC码的准循环构造

系统级仿真与性能评估

完整的通信系统仿真需要考虑多个因素：信道模型、编码增益、同步误差、实现损耗等。以下Python代码提供了完整的系统级仿真框架。

#!/usr/bin/env python3
# 第12课系统级仿真
import numpy as np
import matplotlib.pyplot as plt
from scipy.special import erfc

def ber_theory_bpsk(snr_db):
    return 0.5 * erfc(np.sqrt(10**(snr_db/10)))

def simulate_system(mod_type='bpsk', coding_gain_db=0, num_bits=50000):
    np.random.seed(42)
    snr_range = np.arange(0, 20)
    ber_sim = []
    for snr_db in snr_range:
        effective_snr = snr_db + coding_gain_db
        snr_lin = 10**(effective_snr/10)
        bits = np.random.randint(0, 2, num_bits)
        symbols = 1 - 2*bits
        noise_std = 1.0 / np.sqrt(2*snr_lin)
        noise = noise_std * np.random.randn(len(symbols))
        rx = symbols + noise
        dec = (rx < 0).astype(int)
        ber = np.sum(bits != dec) / num_bits
        ber_sim.append(max(ber, 1e-7))
    return snr_range, ber_sim

snr, ber_u = simulate_system('bpsk', 0)
_, ber_coded = simulate_system('bpsk', 2)

fig, (ax1, ax2) = plt.subplots(1, 2, figsize=(14, 6))
ax1.semilogy(snr, ber_u, 'c-o', markersize=3, label='未编码')
ax1.semilogy(snr, ber_coded, '#10b981-s', markersize=3, label='编码(+2dB)')
ax1.set_xlabel('Eb/N0 (dB)'); ax1.set_ylabel('BER')
ax1.set_title('第12课：BER仿真'); ax1.legend()
ax1.grid(True, alpha=0.3, which='both'); ax1.set_ylim(1e-7, 1)

snr_range2 = np.arange(0, 25)
throughput = [(1 - ber_theory_bpsk(s)) * 1e6 for s in snr_range2]
ax2.plot(snr_range2, np.array(throughput)/1e6, '#f59e0b', linewidth=2)
ax2.set_xlabel('SNR (dB)'); ax2.set_ylabel('吞吐率 (Mbps)')
ax2.set_title('吞吐率 vs SNR'); ax2.grid(True, alpha=0.3)
plt.tight_layout()
plt.savefig('/var/www/ttl/digital-comm/lesson12_sys.png', dpi=100,
            facecolor='#0f172a', edgecolor='none')
print("系统级仿真图已保存")

Verilog实现细节与优化