第11课：卷积码与Viterbi解码

卷积码与Viterbi解码

卷积码与分组码不同，它具有记忆性——当前输出不仅取决于当前输入，还取决于之前的状态。Viterbi算法是最优的卷积码解码方法，通过网格图搜索最可能的信息序列。

卷积码编码器与网格图

🔧 Verilog实现

// viterbi.v - (7,5)卷积码Viterbi解码器
module viterbi_decoder #(
    parameter TRACE_BACK = 32,
    parameter DATA_W = 1
)(
    input  wire clk, rst_n,
    input  wire [1:0] rx_sym,
    input  wire rx_valid,
    output reg  dec_bit,
    output reg  dec_valid
);
    localparam STATES = 4;
    reg [7:0] path_metric [0:STATES-1];
    reg [7:0] branch_metric [0:STATES-1][0:1];
    reg [TRACE_BACK-1:0] survivor [0:STATES-1];
    reg [$clog2(TRACE_BACK)-1:0] tb_cnt;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            for (integer i=0; i<STATES; i=i+1) path_metric[i] <= 0;
            tb_cnt <= 0;
        end else if (rx_valid) begin
            // Add-Compare-Select (simplified)
            for (integer i=0; i<STATES; i=i+1) begin
                integer prev0=(i>>1), prev1=(i>>1)+2;
                reg [7:0] m0, m1;
                m0 = path_metric[prev0] + branch_metric[i][0];
                m1 = path_metric[prev1] + branch_metric[i][1];
                if (m0 < m1) begin
                    path_metric[i] <= m0;
                    survivor[i] <= {survivor[i][TRACE_BACK-2:1], 1'b0};
                end else begin
                    path_metric[i] <= m1;
                    survivor[i] <= {survivor[i][TRACE_BACK-2:1], 1'b1};
                end
            end
            tb_cnt <= tb_cnt + 1;
        end
    end
endmodule

🐍 Python仿真

#!/usr/bin/env python3
import numpy as np
import matplotlib.pyplot as plt
def viterbi_decode(rx, trellis_next, trellis_out):
    n_state, n_time = len(trellis_next), len(rx)//2
    path = np.full((n_state, n_time+1), np.inf)
    path[0,0] = 0
    for t in range(n_time):
        r = rx[2*t:2*t+2]
        for s in range(n_state):
            for b in range(2):
                ns = trellis_next[s][b]
                out = trellis_out[s][b]
                d = sum((r[i]-out[i])**2 for i in range(2))
                if path[s,t]+d < path[ns,t+1]:
                    path[ns,t+1] = path[s,t]+d
    return path
print("Viterbi decoder ready")

深入分析与设计考量

本课主题在数字通信系统中扮演关键角色。理解其设计权衡对构建高效通信系统至关重要。在实际工程中，需要在性能、复杂度和资源之间找到最优平衡点。

与其他模块的接口设计

在完整的通信系统中，本课模块需要与上下游模块正确对接。接口设计遵循AXI-Stream协议：tdata(数据)、tvalid(有效)、tready(就绪)、tlast(包结束)。这种握手协议保证了模块间的数据流控制，避免数据丢失。

Viterbi算法的硬件架构

系统级仿真与性能评估

完整的通信系统仿真需要考虑多个因素：信道模型、编码增益、同步误差、实现损耗等。以下Python代码提供了完整的系统级仿真框架。

#!/usr/bin/env python3
# 第11课系统级仿真
import numpy as np
import matplotlib.pyplot as plt
from scipy.special import erfc

def ber_theory_bpsk(snr_db):
    return 0.5 * erfc(np.sqrt(10**(snr_db/10)))

def simulate_system(mod_type='bpsk', coding_gain_db=0, num_bits=50000):
    np.random.seed(42)
    snr_range = np.arange(0, 20)
    ber_sim = []
    for snr_db in snr_range:
        effective_snr = snr_db + coding_gain_db
        snr_lin = 10**(effective_snr/10)
        bits = np.random.randint(0, 2, num_bits)
        symbols = 1 - 2*bits
        noise_std = 1.0 / np.sqrt(2*snr_lin)
        noise = noise_std * np.random.randn(len(symbols))
        rx = symbols + noise
        dec = (rx < 0).astype(int)
        ber = np.sum(bits != dec) / num_bits
        ber_sim.append(max(ber, 1e-7))
    return snr_range, ber_sim

snr, ber_u = simulate_system('bpsk', 0)
_, ber_coded = simulate_system('bpsk', 2)

fig, (ax1, ax2) = plt.subplots(1, 2, figsize=(14, 6))
ax1.semilogy(snr, ber_u, 'c-o', markersize=3, label='未编码')
ax1.semilogy(snr, ber_coded, '#10b981-s', markersize=3, label='编码(+2dB)')
ax1.set_xlabel('Eb/N0 (dB)'); ax1.set_ylabel('BER')
ax1.set_title('第11课：BER仿真'); ax1.legend()
ax1.grid(True, alpha=0.3, which='both'); ax1.set_ylim(1e-7, 1)

snr_range2 = np.arange(0, 25)
throughput = [(1 - ber_theory_bpsk(s)) * 1e6 for s in snr_range2]
ax2.plot(snr_range2, np.array(throughput)/1e6, '#f59e0b', linewidth=2)
ax2.set_xlabel('SNR (dB)'); ax2.set_ylabel('吞吐率 (Mbps)')
ax2.set_title('吞吐率 vs SNR'); ax2.grid(True, alpha=0.3)
plt.tight_layout()
plt.savefig('/var/www/ttl/digital-comm/lesson11_sys.png', dpi=100,
            facecolor='#0f172a', edgecolor='none')
print("系统级仿真图已保存")

Verilog实现细节与优化