📦 第06课：同步FIFO回顾

五、可编程满/空标志

在实际应用中，FIFO的使用者通常需要提前知道FIFO"快满了"或"快空了"，以便提前做出反应。这就是可编程满（Programmable Full）和可编程空（Programmable Empty）：

// programmable_flags.v
// 可编程满/空标志生成器
// 当FIFO中元素个数达到/低于阈值时置位
module programmable_flags #(
    parameter ADDR_WIDTH = 4,
    parameter PROG_FULL_THRESH  = 12,  // 可编程满阈值
    parameter PROG_EMPTY_THRESH = 4    // 可编程空阈值
)(
    input  wire [ADDR_WIDTH:0] count,
    output wire                prog_full,
    output wire                prog_empty,
    output wire                almost_full,   // 差1个满
    output wire                almost_empty   // 差1个空
);

    assign prog_full  = (count >= PROG_FULL_THRESH);
    assign prog_empty = (count <= PROG_EMPTY_THRESH);
    assign almost_full  = (count >= (1 << ADDR_WIDTH) - 1);
    assign almost_empty = (count <= 1);

endmodule

六、FIFO深度计算

七、同步FIFO的时序分析

八、同步FIFO仿真测试

// tb_sync_fifo.v
// 同步FIFO完整测试台
\`timescale 1ns/1ps

module tb_sync_fifo;

    reg         clk, rst_n;
    reg  [7:0]  wr_data;
    reg         wr_en;
    wire        full;
    wire [7:0]  rd_data;
    reg         rd_en;
    wire        empty;
    wire [4:0]  wr_ptr, rd_ptr, count;

    sync_fifo #(
        .DATA_WIDTH(8),
        .ADDR_WIDTH(4)
    ) uut (
        .clk(clk), .rst_n(rst_n),
        .wr_data(wr_data), .wr_en(wr_en), .full(full),
        .rd_data(rd_data), .rd_en(rd_en), .empty(empty),
        .wr_ptr(wr_ptr), .rd_ptr(rd_ptr), .count(count)
    );

    initial clk = 0;
    always #5 clk = ~clk;

    integer i, errors;

    initial begin
        $dumpfile("sync_fifo.vcd");
        $dumpvars(0, tb_sync_fifo);

        rst_n = 0; wr_en = 0; rd_en = 0; wr_data = 0;
        errors = 0;
        #20 rst_n = 1;
        #10;

        // 测试1: 写满再读空
        $display("--- Test 1: Fill and drain ---");
        for (i = 0; i < 16; i = i + 1) begin
            wr_data = i;
            wr_en = 1;
            @(posedge clk);
        end
        wr_en = 0;
        if (!full) begin
            $display("ERROR: FIFO should be full!");
            errors = errors + 1;
        end

        for (i = 0; i < 16; i = i + 1) begin
            rd_en = 1;
            @(posedge clk);
            if (rd_data !== i) begin
                $display("ERROR: Read data mismatch! Got %0d, expected %0d", rd_data, i);
                errors = errors + 1;
            end
        end
        rd_en = 0;
        if (!empty) begin
            $display("ERROR: FIFO should be empty!");
            errors = errors + 1;
        end

        // 测试2: 同时读写
        $display("--- Test 2: Simultaneous read/write ---");
        wr_en = 1; rd_en = 1;
        for (i = 0; i < 20; i = i + 1) begin
            wr_data = i + 100;
            @(posedge clk);
        end
        wr_en = 0; rd_en = 0;

        // 测试3: 背压测试
        $display("--- Test 3: Backpressure ---");
        rd_en = 0;  // 不读
        for (i = 0; i < 16; i = i + 1) begin
            wr_data = i + 200;
            wr_en = 1;
            @(posedge clk);
        end
        // 尝试写满后的第17次
        wr_data = 8'hFF; wr_en = 1;
        @(posedge clk);
        wr_en = 0;
        // 读出验证
        rd_en = 1;
        for (i = 0; i < 16; i = i + 1) begin
            @(posedge clk);
            if (rd_data !== (i + 200)) begin
                $display("ERROR: Backpressure data mismatch at i=%0d", i);
                errors = errors + 1;
            end
        end
        rd_en = 0;

        #100;
        $display("=== Sync FIFO Test Complete: %0d errors ===", errors);
        $finish;
    end

endmodule

九、Show-ahead FIFO变体

标准FIFO（普通模式）在读使能有效后的下一个时钟沿才输出数据。Show-ahead FIFO（也称为First-Word Fall-Through, FWFT）会自动预取第一个数据，无需读使能即可看到队头：

// sync_fifo_fwft.v
// Show-ahead (First-Word Fall-Through) 同步FIFO
// 数据始终在输出端可用，rd_en作为确认信号
module sync_fifo_fwft #(
    parameter DATA_WIDTH = 8,
    parameter ADDR_WIDTH = 4
)(
    input  wire                  clk,
    input  wire                  rst_n,
    input  wire [DATA_WIDTH-1:0] wr_data,
    input  wire                  wr_en,
    output wire                  full,
    output wire [DATA_WIDTH-1:0] rd_data,
    input  wire                  rd_en,
    output wire                  empty
);

    reg [DATA_WIDTH-1:0] mem [0:(1<