第03课: 帧缓冲

// 第03课: 帧缓冲 - 写像素读回正确 // 第3课: 帧缓冲 - 写像素读回正确 module framebuffer ( input wire clk, input wire rst_n, input wire [15:0] write_addr, input wire [3:0] write_data, input wire write_en, input wire [15:0] read_addr, output reg [3:0] read_data, output reg valid ); // 64x48 = 3072 nibbles (4-bit pixels, 16 colors) reg [3:0] mem [0:3071]; integer i; initial begin for (i = 0; i < 3072; i = i + 1) mem[i] = 4'h0; end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin read_data <= 0; valid <= 0; read_data <= 0; valid <= 0; end else begin if (write_en && write_addr < 3072) mem[write_addr] <= write_data; if (read_addr < 3072) begin read_data <= mem[read_addr]; valid <= 1; end else begin read_data <= 0; valid <= 0; end end end endmodule

/* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off UNOPTFLAT */ /* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off UNOPTFLAT */ module tb; reg clk, rst_n; reg [15:0] write_addr, read_addr; reg [3:0] write_data; reg write_en; wire [3:0] read_data; wire valid; framebuffer uut ( .clk(clk), .rst_n(rst_n), .write_addr(write_addr), .write_data(write_data), .write_en(write_en), .read_addr(read_addr), .read_data(read_data), .valid(valid) ); always clk = #10 ~clk; integer i, errors; initial begin $dumpfile("sim.vcd"); $dumpvars(0, tb); clk = 0; rst_n = 0; write_en = 0; write_addr = 0; write_data = 0; read_addr = 0; repeat(5) @(posedge clk); rst_n = 1; $display("=== 帧缓冲仿真 ==="); $display("写像素读回正确"); $display(""); // Test 1: Write and read back individual pixels $display("--- 测试1: 写入读回 ---"); errors = 0; for (i = 0; i < 16; i = i + 1) begin write_addr = i * 10; write_data = i[3:0]; write_en = 1; @(posedge clk); end write_en = 0; repeat(2) @(posedge clk); for (i = 0; i < 16; i = i + 1) begin read_addr = i * 10; @(posedge clk); @(posedge clk); if (read_data !== i[3:0]) begin $display(" ❌ 地址%0d: 写入%0d 读回%0d", i*10, i, read_data); errors = errors + 1; end end if (errors == 0) $display(" ✅ 16个像素写入读回全部正确"); else $display(" ❌ 有%0d个错误", errors); // Test 2: Fill pattern $display(""); $display("--- 测试2: 填充测试 ---"); for (i = 0; i < 64; i = i + 1) begin write_addr = i; write_data = i[3:0] + 4'h1; write_en = 1; @(posedge clk); end write_en = 0; repeat(2) @(posedge clk); errors = 0; for (i = 0; i < 64; i = i + 1) begin read_addr = i; @(posedge clk); @(posedge clk); if (read_data !== (i[3:0] + 4'h1)) errors = errors + 1; end if (errors == 0) $display(" ✅ 64像素填充写入读回正确"); else $display(" ❌ 填充测试有%0d个错误", errors); // Test 3: Overwrite test $display(""); $display("--- 测试3: 覆盖写入 ---"); write_addr = 100; write_data = 4'hA; write_en = 1; @(posedge clk); write_data = 4'h5; @(posedge clk); write_en = 0; repeat(2) @(posedge clk); read_addr = 100; @(posedge clk); @(posedge clk); if (read_data == 4'h5) $display(" ✅ 覆盖写入正确(旧值=A, 新值=5)"); else $display(" ❌ 覆盖写入错误(期望5, 实际%0d)", read_data); // Test 4: Valid signal $display(""); $display("--- 测试4: 有效信号 ---"); read_addr = 0; @(posedge clk); @(posedge clk); if (valid) $display(" ✅ 有效地址valid=1"); else $display(" ❌ 有效地址valid应为1"); // Test 5: Boundary $display(""); $display("--- 测试5: 边界地址 ---"); write_addr = 3071; write_data = 4'hF; write_en = 1; @(posedge clk); write_en = 0; repeat(2) @(posedge clk); read_addr = 3071; @(posedge clk); @(posedge clk); if (read_data == 4'hF) $display(" ✅ 最高地址3071读写正确"); else $display(" ❌ 最高地址读写错误(期望F, 实际%0h)", read_data); $display(""); $display("✅ 写像素读回正确验证通过!"); $display("🏆 成就解锁: 写像素读回正确!"); $finish; end endmodule

# 编译 verilator --cc *.sv --exe sim_main.cpp --top-module tb --timing --trace \ --build -j 4 -o sim \ -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-UNOPTFLAT \ -Wno-TIMESCALEMOD -Wno-STMTDLY -Wno-WIDTH \ -Wno-UNSIGNED -Wno-SELRANGE -Wno-BLKLOOPINIT # 运行 ./obj_dir/sim # 查看波形(可选) gtkwave sim.vcd