//==================================================================== // complete_gpu_pipeline.v - 完整GPU管线 // 第30课：全管线集成与验证 //==================================================================== module complete_gpu_pipeline #( parameter COORD_WIDTH = 16, parameter COLOR_WIDTH = 24, parameter DEPTH_WIDTH = 16, parameter FB_WIDTH = 640, parameter FB_HEIGHT = 480, parameter FRAC_BITS = 12, parameter TEX_SIZE = 128, parameter MAX_LIGHTS = 2 )( input wire clk, rst_n, // 命令接口 input wire cmd_valid, input wire [3:0] cmd_type, // 0=DRAW_TRI, 1=SET_MATRIX, 2=SET_LIGHT, 3=CLEAR, 4=FLIP input wire [127:0] cmd_data, output reg cmd_ready, // 帧缓冲输出 output reg fb_wen, output reg [COORD_WIDTH-1:0] fb_x, fb_y, output reg [COLOR_WIDTH-1:0] fb_color, // VGA接口 output reg vga_hsync, vga_vsync, output reg [7:0] vga_r, vga_g, vga_b, output reg vga_de, output reg frame_done, // 状态 output reg [3:0] pipeline_stage, output reg [31:0] stat_vertices, output reg [31:0] stat_triangles, output reg [31:0] stat_fragments ); /* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off CASEOVERLAP */ /* verilator lint_off CMPCONST */ /* verilator lint_off UNSIGNED */ /* verilator lint_off WIDTHCONCAT */ function signed [COORD_WIDTH-1:0] qmul; input signed [COORD_WIDTH-1:0] a, b; reg signed [2*COORD_WIDTH-1:0] prod; begin prod = a * b; qmul = prod[2*COORD_WIDTH-FRAC_BITS-1:COORD_WIDTH-FRAC_BITS]; end endfunction // 变换矩阵 reg signed [COORD_WIDTH-1:0] mvp_mat [0:3][0:3]; // 顶点处理缓冲 reg signed [COORD_WIDTH-1:0] vert_buf_x [0:2], vert_buf_y [0:2], vert_buf_z [0:2]; reg [COLOR_WIDTH-1:0] vert_buf_color [0:2]; reg [1:0] vert_count; // 深度缓冲(简化: 256项) reg signed [DEPTH_WIDTH-1:0] zbuf [0:255]; // 统计 reg [31:0] vert_cnt, tri_cnt, frag_cnt; // 完整管线状态 localparam ST_IDLE=4'd0, ST_RECV_VERT=4'd1, ST_TRANSFORM=4'd2, ST_ASSEMBLE=4'd3, ST_CULL=4'd4, ST_CLIP=4'd5, ST_RASTER=4'd6, ST_SHADE=4'd7, ST_DEPTH_TEST=4'd8, ST_BLEND=4'd9, ST_FB_WRITE=4'd10, ST_DONE=4'd11, ST_CLEAR=4'd12; reg [3:0] pstate; // 光栅化扫描 reg [COORD_WIDTH-1:0] scan_x, scan_y; reg signed [COORD_WIDTH-1:0] tri_min_x, tri_max_x, tri_min_y, tri_max_y; reg signed [2*COORD_WIDTH-1:0] det, lam0, lam1; reg signed [COORD_WIDTH-1:0] dy12, dx12, dy20, dx20; // 光照 reg signed [COORD_WIDTH-1:0] light_dir [0:MAX_LIGHTS-1][0:2]; reg [COLOR_WIDTH-1:0] light_col [0:MAX_LIGHTS-1]; // VGA时序 reg [9:0] h_cnt, v_cnt; localparam H_TOTAL=800, V_TOTAL=525; // 清屏 reg [COORD_WIDTH-1:0] clear_x, clear_y; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin pstate<=ST_IDLE; cmd_ready<=1; fb_wen<=0; frame_done<=0; pipeline_stage<=0; vert_count<=0; vert_cnt<=0; tri_cnt<=0; frag_cnt<=0; stat_vertices<=0; stat_triangles<=0; stat_fragments<=0; vga_hsync<=1; vga_vsync<=1; vga_de<=0; vga_r<=0; vga_g<=0; vga_b<=0; h_cnt<=0; v_cnt<=0; end else begin fb_wen <= 0; frame_done <= 0; // VGA时序(持续运行) if (h_cnt == H_TOTAL - 1) begin h_cnt <= 0; if (v_cnt == V_TOTAL - 1) v_cnt <= 0; else v_cnt <= v_cnt + 1; end else h_cnt <= h_cnt + 1; vga_hsync <= (h_cnt >= 656 && h_cnt < 752) ? 1'b0 : 1'b1; vga_vsync <= (v_cnt >= 490 && v_cnt < 492) ? 1'b0 : 1'b1; vga_de <= (h_cnt < 640 && v_cnt < 480); // 主状态机 case (pstate) ST_IDLE: begin cmd_ready <= 1; pipeline_stage <= 4'd0; if (cmd_valid) begin cmd_ready <= 0; case (cmd_type) 4'd0: pstate <= ST_RECV_VERT; // DRAW_TRI 4'd3: begin clear_x<=0; clear_y<=0; pstate<=ST_CLEAR; end 4'd4: begin frame_done<=1; pstate<=ST_IDLE; end default: pstate <= ST_IDLE; endcase end end ST_CLEAR: begin fb_wen <= 1; fb_x <= clear_x; fb_y <= clear_y; fb_color <= 24'h000033; zbuf[{4'b0, clear_y[7:0], clear_x[7:0]}] <= 16'h7FFF; if (clear_x < FB_WIDTH - 1) clear_x <= clear_x + 1; else begin clear_x <= 0; if (clear_y < FB_HEIGHT - 1) clear_y <= clear_y + 1; else pstate <= ST_IDLE; end end ST_RECV_VERT: begin // 从cmd_data接收顶点 vert_buf_x[vert_count] <= cmd_data[15:0]; vert_buf_y[vert_count] <= cmd_data[31:16]; vert_buf_z[vert_count] <= cmd_data[47:32]; vert_buf_color[vert_count] <= cmd_data[71:48]; if (vert_count == 2) begin vert_count<=0; pstate<=ST_TRANSFORM; end else vert_count <= vert_count + 1; end ST_TRANSFORM: begin // MVP变换(简化：直通) vert_cnt <= vert_cnt + 1; stat_vertices <= stat_vertices + 1; pstate <= ST_ASSEMBLE; end ST_ASSEMBLE: begin tri_cnt <= tri_cnt + 1; stat_triangles <= stat_triangles + 1; pstate <= ST_CULL; end ST_CULL: begin // 简化背面剔除 dy12 <= vert_buf_y[1] - vert_buf_y[2]; dx12 <= vert_buf_x[2] - vert_buf_x[1]; dy20 <= vert_buf_y[2] - vert_buf_y[0]; dx20 <= vert_buf_x[0] - vert_buf_x[2]; det <= (vert_buf_y[1]-vert_buf_y[2])*(vert_buf_x[0]-vert_buf_x[2]) + (vert_buf_x[2]-vert_buf_x[1])*(vert_buf_y[0]-vert_buf_y[2]); pstate <= ST_CLIP; end ST_CLIP: begin tri_min_x <= (vert_buf_x[0]vert_buf_x[1])?((vert_buf_x[0]>vert_buf_x[2])?vert_buf_x[0]:vert_buf_x[2]):((vert_buf_x[1]>vert_buf_x[2])?vert_buf_x[1]:vert_buf_x[2]); tri_min_y <= (vert_buf_y[0]vert_buf_y[1])?((vert_buf_y[0]>vert_buf_y[2])?vert_buf_y[0]:vert_buf_y[2]):((vert_buf_y[1]>vert_buf_y[2])?vert_buf_y[1]:vert_buf_y[2]); scan_x <= tri_min_x; scan_y <= tri_min_y; pstate <= ST_RASTER; end ST_RASTER: begin if (scan_y <= tri_max_y) begin if (scan_x <= tri_max_x) begin lam0 <= dy12*(scan_x-vert_buf_x[2]) + dx12*(scan_y-vert_buf_y[2]); lam1 <= dy20*(scan_x-vert_buf_x[2]) + dx20*(scan_y-vert_buf_y[2]); pstate <= ST_SHADE; end else begin scan_x <= tri_min_x; scan_y <= scan_y + 1; end end else pstate <= ST_DONE; end ST_SHADE: begin frag_cnt <= frag_cnt + 1; stat_fragments <= stat_fragments + 1; pstate <= ST_DEPTH_TEST; end ST_DEPTH_TEST: begin // 简化：总是通过 pstate <= ST_FB_WRITE; end ST_FB_WRITE: begin fb_wen <= 1; fb_x <= scan_x; fb_y <= scan_y; fb_color <= vert_buf_color[0]; scan_x <= scan_x + 1; pstate <= ST_RASTER; end ST_DONE: begin pstate <= ST_IDLE; end default: pstate <= ST_IDLE; endcase end end endmodule