//====================================================================
// alpha_blender.v - Alpha混合器
// 第21课：源/目标因子混合
//====================================================================
module alpha_blender #(
    parameter COLOR_WIDTH = 24
)(
    input  wire                          clk, rst_n,
    input  wire                          blend_valid,
    input  wire [7:0]                    src_r, src_g, src_b, src_a,
    input  wire [7:0]                    dst_r, dst_g, dst_b, dst_a,
    input  wire [3:0]                    src_factor,  // 0=ZERO,1=ONE,2=SRC_ALPHA,3=ONE_MINUS_SRC_ALPHA
    input  wire [3:0]                    dst_factor,
    output reg                           blend_ready,
    output reg  [7:0]                    out_r, out_g, out_b, out_a,
    output reg                           result_valid
);
/* verilator lint_off WIDTHEXPAND */
/* verilator lint_off WIDTHTRUNC */
/* verilator lint_off CASEOVERLAP */
/* verilator lint_off CMPCONST */
/* verilator lint_off UNSIGNED */
/* verilator lint_off WIDTHCONCAT */

    reg [15:0] sf_r, sf_g, sf_b, sf_a;
    reg [15:0] df_r, df_g, df_b, df_a;
    reg [15:0] s_r, s_g, s_b, d_r, d_g, d_b;
    localparam S_IDLE=2'd0, S_FACTOR=2'd1, S_BLEND=2'd2, S_OUT=2'd3;
    reg [1:0] state;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin state<=S_IDLE; blend_ready<=1; result_valid<=0; end
        else begin
            result_valid <= 0;
            case (state)
                S_IDLE: begin
                    blend_ready <= 1;
                    if (blend_valid) begin blend_ready <= 0; state <= S_FACTOR; end
                end
                S_FACTOR: begin
                    case (src_factor)
                        4'd0: begin sf_r<=16'd0; sf_g<=16'd0; sf_b<=16'd0; sf_a<=16'd0; end
                        4'd1: begin sf_r<={src_r,8'b0}; sf_g<={src_g,8'b0}; sf_b<={src_b,8'b0}; sf_a<={src_a,8'b0}; end
                        4'd2: begin sf_r<={src_a,src_a}; sf_g<={src_a,src_a}; sf_b<={src_a,src_a}; sf_a<={src_a,src_a}; end
                        4'd3: begin sf_r<={(8'd255-src_a),src_r}; sf_g<={(8'd255-src_a),src_g}; sf_b<={(8'd255-src_a),src_b}; sf_a<={(8'd255-src_a),src_a}; end
                        default: begin sf_r<={src_r,8'b0}; sf_g<={src_g,8'b0}; sf_b<={src_b,8'b0}; sf_a<={src_a,8'b0}; end
                    endcase
                    case (dst_factor)
                        4'd0: begin df_r<=16'd0; df_g<=16'd0; df_b<=16'd0; df_a<=16'd0; end
                        4'd1: begin df_r<={dst_r,8'b0}; df_g<={dst_g,8'b0}; df_b<={dst_b,8'b0}; df_a<={dst_a,8'b0}; end
                        4'd2: begin df_r<={src_a,dst_r}; df_g<={src_a,dst_g}; df_b<={src_a,dst_b}; df_a<={src_a,dst_a}; end
                        4'd3: begin df_r<={(8'd255-src_a),dst_r}; df_g<={(8'd255-src_a),dst_g}; df_b<={(8'd255-src_a),dst_b}; df_a<={(8'd255-src_a),dst_a}; end
                        default: begin df_r<={dst_r,8'b0}; df_g<={dst_g,8'b0}; df_b<={dst_b,8'b0}; df_a<={dst_a,8'b0}; end
                    endcase
                    state <= S_BLEND;
                end
                S_BLEND: begin
                    s_r = (src_r * sf_r) >> 8; s_g = (src_g * sf_g) >> 8; s_b = (src_b * sf_b) >> 8;
                    d_r = (dst_r * df_r) >> 8; d_g = (dst_g * df_g) >> 8; d_b = (dst_b * df_b) >> 8;
                    out_r <= (s_r + d_r > 255) ? 8'd255 : s_r[7:0] + d_r[7:0];
                    out_g <= (s_g + d_g > 255) ? 8'd255 : s_g[7:0] + d_g[7:0];
                    out_b <= (s_b + d_b > 255) ? 8'd255 : s_b[7:0] + d_b[7:0];
                    out_a <= 8'd255;
                    state <= S_OUT;
                end
                S_OUT: begin
                    result_valid <= 1; state <= S_IDLE;
                end
                default: state <= S_IDLE;
            endcase
        end
    end
endmodule