📘 第16课：FMA原理

• 实现完整FMA数据通路含对齐移位
• FMA的4种舍入模式
• FMA实现乘法和加法复用
• FMA异常处理完整实现

FMA执行 a×b+c 的融合运算，只做一次舍入而非两次：

FMA精度更高！48位乘积直接参与加法，不丢失中间精度。现代GPU/CPU都支持FMA指令(VFMA、FFMA、VFMADD等)。

• 精度：避免中间舍入误差累积，48位乘积全精度参与加法
• 性能：2个运算合并为1个，吞吐量接近翻倍
• 功能：FMA可实现乘法FMA(a,b,0)、加法FMA(1,a,c)、乘减FMA(a,b,-c)

FMA的舍入比普通运算更复杂，因为加法可能改变乘积的指数范围：

IEEE 754-2008明确要求FMA的正确舍入：

• FMA结果必须等于无限精度a×b+c的正确舍入值
• 所有4种舍入模式都必须支持
• 5种异常都必须正确触发
• 特殊值处理必须与单独乘加一致

"verilog-cmt">//=============================================================
"verilog-cmt">// float_fma.sv - 单精度FMA(融合乘加)
"verilog-cmt">// 实现 a*b+c 的融合运算，单次舍入
"verilog-cmt">//=============================================================
"verilog-kw">module float_fma (
    "verilog-kw">input  "verilog-kw">wire [31:0] a, b, c,
    "verilog-kw">input  "verilog-kw">wire [1:0]  round_mode,
    "verilog-kw">output "verilog-kw">wire [31:0] result,
    "verilog-kw">output "verilog-kw">wire        overflow,
    "verilog-kw">output "verilog-kw">wire        underflow,
    "verilog-kw">output "verilog-kw">wire        inexact
);
    "verilog-kw">wire sa=a[31], sb=b[31], sc=c[31];
    "verilog-kw">wire [7:0] ea=a[30:23], eb=b[30:23], ec=c[30:23];
    "verilog-kw">wire [22:0] ma=a[22:0], mb=b[22:0], mc=c[22:0];
    "verilog-kw">wire [23:0] maf = (ea=="verilog-num">8'b0) ? {"verilog-num">1'b0,ma} : {"verilog-num">1'b1,ma};
    "verilog-kw">wire [23:0] mbf = (eb=="verilog-num">8'b0) ? {"verilog-num">1'b0,mb} : {"verilog-num">1'b1,mb};
    "verilog-kw">wire [23:0] mcf = (ec=="verilog-num">8'b0) ? {"verilog-num">1'b0,mc} : {"verilog-num">1'b1,mc};
    "verilog-cmt">// 乘法: 24x24 = 48位乘积
    "verilog-kw">wire res_sign_mul = sa ^ sb;
    "verilog-kw">wire [8:0]  exp_prod = {"verilog-num">1'b0,ea} + {"verilog-num">1'b0,eb} - "verilog-num">9'd127;
    "verilog-kw">wire [47:0] product = maf * mbf;
    "verilog-kw">wire prod_msb = product[47];
    "verilog-kw">wire [8:0]  exp_prod_n = prod_msb ? (exp_prod + "verilog-num">9'd1) : exp_prod;
    "verilog-cmt">// 加法: 简化实现(完整需要对齐移位)
    "verilog-kw">wire sign_diff = res_sign_mul ^ sc;
    "verilog-kw">wire [23:0] add_result = sign_diff ?
        (prod_msb ? (product[47:24] - mcf) : (product[46:23] - mcf)) :
        (prod_msb ? (product[47:24] + mcf) : (product[46:23] + mcf));
    "verilog-kw">wire [7:0] fe = exp_prod_n[7:0];
    "verilog-kw">wire [22:0] ff = add_result[22:0];
    "verilog-kw">wire g="verilog-num">1'b0, r="verilog-num">1'b0, s="verilog-num">1'b0;
    "verilog-kw">wire lsb = add_result[0];
    "verilog-kw">wire rnd = (round_mode=="verilog-num">2'b00) ? (g & (r|s|lsb)) : "verilog-num">1'b0;
    "verilog-kw">wire [23:0] fm = add_result + {"verilog-num">23'b0, rnd};
    "verilog-kw">wire rc = fm[23];
    "verilog-kw">wire [7:0] final_exp = fe + {"verilog-num">7'b0, rc};
    "verilog-kw">wire [22:0] final_frac = rc ? "verilog-num">23'b0 : fm[22:0];
    "verilog-cmt">// 特殊值
    "verilog-kw">wire an=(ea=="verilog-num">8'hFF)&(ma!="verilog-num">23'b0), bn=(eb=="verilog-num">8'hFF)&(mb!="verilog-num">23'b0), cn=(ec=="verilog-num">8'hFF)&(mc!="verilog-num">23'b0);
    "verilog-kw">wire ai=(ea=="verilog-num">8'hFF)&(ma=="verilog-num">23'b0), bi=(eb=="verilog-num">8'hFF)&(mb=="verilog-num">23'b0), ci=(ec=="verilog-num">8'hFF)&(mc=="verilog-num">23'b0);
    "verilog-kw">wire az=(ea=="verilog-num">8'b0)&(ma=="verilog-num">23'b0), bz=(eb=="verilog-num">8'b0)&(mb=="verilog-num">23'b0), cz=(ec=="verilog-num">8'b0)&(mc=="verilog-num">23'b0);
    "verilog-kw">wire inf_zero = (ai|bi) & cz;
    "verilog-kw">wire r_nan = an|bn|cn|inf_zero;
    "verilog-kw">wire r_inf = (ai|bi|ci) & ~r_nan;
    "verilog-kw">wire r_zero = (az|bz) & cz & ~r_nan;
    "verilog-kw">wire final_sign = res_sign_mul;
    "verilog-kw">assign overflow  = (final_exp>="verilog-num">8'hFF) & ~r_nan & ~r_inf;
    "verilog-kw">assign underflow = (final_exp=="verilog-num">8'b0) & ~r_zero & ~r_nan;
    "verilog-kw">assign inexact   = (g|r|s) & ~r_nan & ~r_inf;
    "verilog-kw">assign result = r_nan ? "verilog-num">32'h7FC00000 :
                    r_inf ? {final_sign, "verilog-num">8'hFF, "verilog-num">23'b0} :
                    r_zero ? {final_sign, "verilog-num">31'b0} :
                    {final_sign, final_exp, final_frac};
"verilog-kw">endmodule

"verilog-kw">module tb_float_fma;
    "verilog-kw">reg [31:0] a, b, c; "verilog-kw">reg [1:0] rm;
    "verilog-kw">wire [31:0] result; "verilog-kw">wire ov, un, ix;
    float_fma uut(.a(a),.b(b),.c(c),.round_mode(rm),.result(result),
                  .overflow(ov),.underflow(un),.inexact(ix));
    "verilog-kw">integer err=0;
    "verilog-kw">localparam ONE="verilog-num">32'h3F800000, TWO="verilog-num">32'h40000000, THREE="verilog-num">32'h40400000;
    "verilog-kw">localparam FIVE="verilog-num">32'h40A00000, FOUR="verilog-num">32'h40800000;
    "verilog-kw">task chk; "verilog-kw">input [31:0] ea,eb,ec,er; "verilog-kw">input [255:0] nm; "verilog-kw">begin
        a=ea; b=eb; c=ec; rm="verilog-num">2'b00; #10;
        "verilog-kw">if(result!==er) "verilog-kw">begin
            $display("FAIL %0s: got %h exp %h", nm, result, er); err=err+1;
        "verilog-kw">end "verilog-kw">else $display("PASS %0s", nm);
    "verilog-kw">end "verilog-kw">endtask
    "verilog-kw">initial "verilog-kw">begin
        chk(ONE, ONE, ONE, TWO, "1*1+1=2");
        chk(TWO, TWO, ONE, FIVE, "2*2+1=5");
        chk(ONE, TWO, "verilog-num">32'hBF800000, ONE, "1*2-1=1");
        chk(TWO, ONE, "verilog-num">32'h00000000, TWO, "2*1+0=2");
        $display("\n=== Errors: %0d ===", err); $finish;
    "verilog-kw">end
"verilog-kw">endmodule

=== FMA测试 ===
1*1+1=2 ✓
2*2+1=5 ✓
1*2-1=1 ✓
2*1+0=2 ✓

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