📺 第2课：VGA信号

module vga_sync (
    input  wire clk,        // 25MHz像素时钟
    input  wire rst_n,
    output reg  hsync, vsync,
    output reg  [9:0] hcount, vcount,
    output wire video_on
);
    localparam H_TOTAL=800, H_VISIBLE=640, H_FRONT=16, H_SYNC=96, H_BACK=48;
    localparam V_TOTAL=525, V_VISIBLE=480, V_FRONT=10, V_SYNC=2,  V_BACK=33;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) hcount <= 0;
        else if (hcount == H_TOTAL-1) hcount <= 0;
        else hcount <= hcount + 1;
    end

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) vcount <= 0;
        else if (hcount == H_TOTAL-1) begin
            if (vcount == V_TOTAL-1) vcount <= 0;
            else vcount <= vcount + 1;
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) hsync <= 1;
        else hsync <= ~((hcount >= H_VISIBLE+H_FRONT) &&
                        (hcount < H_VISIBLE+H_FRONT+H_SYNC));
    end

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) vsync <= 1;
        else vsync <= ~((vcount >= V_VISIBLE+V_FRONT) &&
                        (vcount < V_VISIBLE+V_FRONT+V_SYNC));
    end

    assign video_on = (hcount < H_VISIBLE) && (vcount < V_VISIBLE);
endmodule

module vga_sync_tb;
    logic clk,rst_n; logic hsync,vsync,video_on;
    logic [9:0] hcount,vcount;
    vga_sync uut(.*);
    initial clk=0; always #20 clk=~clk; // 25MHz

    // HSYNC低脉冲宽度统计
    int hsync_low, hsync_edges;
    logic hsync_prev;
    always @(posedge clk) begin
        hsync_prev<=hsync;
        if(!hsync) hsync_low++;
        else if(hsync&&!hsync_prev&&hsync_low>0) begin
            if(hsync_low!=96) $display("FAIL:HSYNC=%0d",hsync_low);
            else $display("  HSYNC脉冲=%0d像素 ✓",hsync_low);
            hsync_low<=0; hsync_edges++;
        end
    end

    // VSYNC低脉冲统计
    int vsync_low;
    logic vsync_prev;
    always @(posedge clk) begin
        vsync_prev<=vsync;
        if(!vsync) vsync_low++;
        else if(vsync&&!vsync_prev&&vsync_low>0) begin
            if(vsync_low!=1600) $display("FAIL:VSYNC=%0d",vsync_low);
            else $display("  VSYNC脉冲=%0d像素时钟(2行) ✓",vsync_low);
            vsync_low<=0;
        end
    end

    // 帧计数和有效像素统计
    int frame_count=0, video_on_count;
    logic vsync_fell;
    always @(posedge clk) begin
        vsync_fell<=!vsync&&vsync_prev;
        if(video_on) video_on_count++;
        if(vsync_fell) begin
            if(frame_count>0) begin
                if(video_on_count==640*480)
                    $display("  帧%0d: 有效像素=%0d ✓",frame_count,video_on_count);
                else
                    $display("  FAIL: 帧%0d像素=%0d",frame_count,video_on_count);
            end
            video_on_count<=0; frame_count++;
        end
    end

    initial begin
        $dumpfile("vga_sync.vcd");$dumpvars(0,vga_sync_tb);
        rst_n=0;#100;rst_n=1;
        $display("========== VGA时序验证 ==========");
        wait(frame_count==4);
        $display("==================================");
        $display("  VGA时序验证完成！");
        $display("  - HSYNC: 96像素 ✓");
        $display("  - VSYNC: 2行 ✓");
        $display("  - 有效: 640×480 ✓");
        $display("==================================");
        $finish;
    end
    initial #200_000_000 $finish;
endmodule

module vga_sync_tb;
    logic clk,rst_n; logic hsync,vsync,video_on;
    logic [9:0] hcount,vcount;
    vga_sync uut(.*);
    initial clk=0; always #20 clk=~clk; // 25MHz
    // 检测HSYNC低脉冲宽度(应为96)
    int hsync_low;
    always @(posedge clk) begin
        if(!hsync) hsync_low++;
        else if(hsync_low>0 && hsync_low!=96)
            $display("FAIL: HSYNC=%0d",hsync_low);
        else if(hsync_low==96) $display("HSYNC=96 ✓");
    end
    initial begin rst_n=0; #100; rst_n=1; #200_000_000; $finish; end
endmodule