🏗️ 毕业项目

// Capstone SoC — 完整片上系统
module capstone_soc (
    input wire clk, rst,
    output wire uart_tx, input wire uart_rx,
    output wire spi_sclk, spi_mosi, spi_cs_n, input wire spi_miso,
    output wire i2c_scl, i2c_sda_out, i2c_sda_oe, input wire i2c_sda_in,
    output wire [9:0] vga_hcount, vga_vcount,
    output wire vga_hsync, vga_vsync,
    output wire [3:0] vga_r, vga_g, vga_b,
    output wire [15:0] audio_out,
    output wire dma_done_irq
);
// Bus
reg [15:0] bus_addr; reg [31:0] bus_wdata; wire [31:0] bus_rdata; reg bus_wr;
// CPU
reg [15:0] pc; reg [31:0] instr_rom [0:255]; reg [31:0] cur_instr; reg [2:0] cpu_st; reg cpu_halted;
initial begin instr_rom[0]=32'h00100001;instr_rom[1]=32'h00140055;instr_rom[2]=32'h002800AA;
instr_rom[3]=32'h0040003C;instr_rom[4]=32'h00500080;instr_rom[5]=32'h00600001;
instr_rom[6]=32'h00000000;instr_rom[7]=32'hFFFFFFFF; end
always @(posedge clk or posedge rst) begin
    if (rst) begin pc<=0;bus_addr<=0;bus_wdata<=0;bus_wr<=0;cpu_halted<=0;cpu_st<=0; end
    else if (!cpu_halted) begin
        bus_wr<=0;
        case (cpu_st)
            0: begin cur_instr<=instr_rom[pc];cpu_st<=1; end
            1: begin if (cur_instr==32'hFFFFFFFF) cpu_halted<=1;
                else begin bus_addr<=cur_instr[31:16];bus_wdata<=cur_instr[15:0];bus_wr<=1;pc<=pc+1; end
                cpu_st<=0; end
            default: cpu_st<=0;
        endcase
    end
end
wire cs_timer=(bus_addr[7:4]==0),cs_uart=(bus_addr[7:4]==1),cs_spi=(bus_addr[7:4]==2);
wire cs_i2c=(bus_addr[7:4]==4),cs_pwm=(bus_addr[7:4]==5),cs_dma=(bus_addr[7:4]==6);
// Timer
reg [31:0] timer_reload,timer_count; reg timer_en; wire timer_irq=timer_en&&timer_count==0;
always @(posedge clk or posedge rst) begin
    if (rst) begin timer_reload<=32'd49999;timer_count<=32'd49999;timer_en<=0; end
    else begin
        if (bus_wr&&cs_timer) case(bus_addr[3:0]) 0:timer_reload<=bus_wdata; 4:timer_en<=bus_wdata[0]; endcase
        if (timer_en) begin if(timer_count==0) timer_count<=timer_reload; else timer_count<=timer_count-1; end
    end
end
// UART TX
typedef enum logic [1:0] {U_IDLE,U_START,U_DATA,U_STOP} uart_st_t;
uart_st_t uart_st; reg [31:0] uart_cnt; reg [2:0] uart_bi; reg [7:0] uart_sh; reg uart_tx_r;
assign uart_tx=uart_tx_r;
always @(posedge clk or posedge rst) begin
    if (rst) begin uart_st<=U_IDLE;uart_tx_r<=1;uart_cnt<=0;uart_bi<=0;uart_sh<=0; end
    else begin case(uart_st)
        U_IDLE: begin uart_tx_r<=1; if(bus_wr&&cs_uart&&bus_addr[3:0]==0) begin uart_sh<=bus_wdata[7:0];uart_st<=U_START;uart_tx_r<=0;uart_cnt<=0; end end
        U_START: if(uart_cnt>=433) begin uart_cnt<=0;uart_bi<=0;uart_st<=U_DATA; end else uart_cnt<=uart_cnt+1;
        U_DATA: begin uart_tx_r<=uart_sh[0]; if(uart_cnt>=433) begin uart_cnt<=0;uart_sh<={1'b0,uart_sh[7:1]}; if(uart_bi==7) uart_st<=U_STOP; else uart_bi<=uart_bi+1; end else uart_cnt<=uart_cnt+1; end
        U_STOP: begin uart_tx_r<=1; if(uart_cnt>=433) begin uart_cnt<=0;uart_st<=U_IDLE; end else uart_cnt<=uart_cnt+1; end
        default: uart_st<=U_IDLE; endcase
    end
end
// SPI
reg [7:0] spi_sh; reg [2:0] spi_bc; reg spi_act,spi_sclk_r,spi_mosi_r,spi_cs_n_r;
assign spi_sclk=spi_sclk_r;assign spi_mosi=spi_mosi_r;assign spi_cs_n=spi_cs_n_r;
always @(posedge clk or posedge rst) begin
    if (rst) begin spi_sh<=0;spi_bc<=0;spi_act<=0;spi_sclk_r<=0;spi_mosi_r<=0;spi_cs_n_r<=1; end
    else begin if(bus_wr&&cs_spi&&!spi_act) begin spi_sh<=bus_wdata[7:0];spi_act<=1;spi_cs_n_r<=0;spi_bc<=0; end
        if(spi_act) begin spi_sclk_r<=~spi_sclk_r; if(spi_sclk_r) begin spi_mosi_r<=spi_sh[7];spi_sh<={spi_sh[6:0],spi_miso}; end
            if(spi_bc==7&&!spi_sclk_r) begin spi_act<=0;spi_cs_n_r<=1; end else if(!spi_sclk_r) spi_bc<=spi_bc+1; end
    end
end
// I2C
reg [7:0] i2c_sh; reg [3:0] i2c_bc; reg i2c_act,i2c_scl_r,i2c_sda_out_r,i2c_sda_oe_r;
assign i2c_scl=i2c_scl_r;assign i2c_sda_out=i2c_sda_out_r;assign i2c_sda_oe=i2c_sda_oe_r;
always @(posedge clk or posedge rst) begin
    if (rst) begin i2c_sh<=0;i2c_bc<=0;i2c_act<=0;i2c_scl_r<=1;i2c_sda_out_r<=0;i2c_sda_oe_r<=0; end
    else begin if(bus_wr&&cs_i2c&&!i2c_act) begin i2c_sh<=bus_wdata[7:0];i2c_act<=1;i2c_bc<=0;i2c_sda_oe_r<=1;i2c_sda_out_r<=0; end
        if(i2c_act) begin i2c_scl_r<=~i2c_scl_r; if(!i2c_scl_r) begin i2c_sda_out_r<=i2c_sh[7];i2c_sh<={i2c_sh[6:0],1'b0}; end
            if(i2c_bc==8) begin i2c_act<=0;i2c_sda_oe_r<=0;i2c_scl_r<=1; end else if(!i2c_scl_r) i2c_bc<=i2c_bc+1; end
    end
end
// PWM
reg [7:0] pwm_cnt,pwm_duty; wire pwm_out=pwm_cnt<pwm_duty;
always @(posedge clk or posedge rst) begin
    if (rst) begin pwm_cnt<=0;pwm_duty<=0; end else begin pwm_cnt<=pwm_cnt+1; if(bus_wr&&cs_pwm) pwm_duty<=bus_wdata[7:0]; end
end
// VGA (simplified, clock divided)
reg vga_div; always @(posedge clk or posedge rst) begin if(rst) vga_div<=0; else vga_div<=~vga_div; end
reg [9:0] vga_h,vga_v; reg vga_hs_r,vga_vs_r; reg [3:0] vga_r_r,vga_g_r,vga_b_r;
assign vga_hcount=vga_h;assign vga_vcount=vga_v;assign vga_hsync=vga_hs_r;assign vga_vsync=vga_vs_r;
assign vga_r=vga_r_r;assign vga_g=vga_g_r;assign vga_b=vga_b_r;
always @(posedge vga_div or posedge rst) begin
    if (rst) begin vga_h<=0;vga_v<=0;vga_hs_r<=1;vga_vs_r<=1;vga_r_r<=0;vga_g_r<=0;vga_b_r<=0; end
    else begin
        if(vga_h>=799) vga_h<=0; else vga_h<=vga_h+1;
        if(vga_h==799) begin if(vga_v>=524) vga_v<=0; else vga_v<=vga_v+1; end
        vga_hs_r<=(vga_h>=656&&vga_h<752)?0:1; vga_vs_r<=(vga_v>=490&&vga_v<492)?0:1;
        if(vga_h<640&&vga_v<480) begin vga_r_r<=vga_h[7:4];vga_g_r<=vga_v[7:4];vga_b_r<={vga_h[5],vga_v[5],vga_h[3],vga_v[3]}; end
        else begin vga_r_r<=0;vga_g_r<=0;vga_b_r<=0; end
    end
end
// Audio
reg [15:0] audio_ch0,audio_ch1,audio_ch2,audio_sum; assign audio_out=audio_sum;
always @(posedge clk or posedge rst) begin
    if (rst) begin audio_ch0<=0;audio_ch1<=0;audio_ch2<=0;audio_sum<=0; end
    else begin audio_ch0<=audio_ch0+16'h0100;audio_ch1<=audio_ch1+16'h0200;audio_ch2<=audio_ch2+16'h0400;
        audio_sum<=audio_ch0[15:1]+audio_ch1[15:1]+audio_ch2[15:1]; end
end
// DMA
reg [15:0] dma_src,dma_dst,dma_len,dma_count; reg dma_act;
assign dma_done_irq=dma_act&&(dma_count>=dma_len);
always @(posedge clk or posedge rst) begin
    if (rst) begin dma_src<=0;dma_dst<=0;dma_len<=0;dma_count<=0;dma_act<=0; end
    else begin if(bus_wr&&cs_dma&&bus_addr[3:0]==4) begin dma_src<=bus_wdata[15:0];dma_dst<=bus_wdata[15:0]+16'h100;dma_len<=16'd16;dma_count<=0;dma_act<=1; end
        if(dma_act&&!dma_done_irq) dma_count<=dma_count+1; if(dma_done_irq) dma_act<=0; end
end
// Bus read mux
assign bus_rdata = cs_timer?{31'd0,timer_irq} : cs_pwm?{24'd0,pwm_duty} : cs_dma?{15'd0,dma_count} : 32'd0;
endmodule