📡 I2C从机

// I2C Slave — I2C从机, 7-bit address
module i2c_slave #(parameter SLAVE_ADDR = 7'h50)(
    input wire clk, rst, scl, sda_in,
    output reg sda_out, sda_oe,
    output reg [7:0] rx_data, output reg rx_valid,
    input wire [7:0] tx_data, output reg addr_match
);
reg scl_s1,scl_s2,scl_s3, sda_s1,sda_s2,sda_s3;
always @(posedge clk or posedge rst) begin
    if (rst) begin scl_s1<=1;scl_s2<=1;scl_s3<=1;sda_s1<=1;sda_s2<=1;sda_s3<=1; end
    else begin scl_s1<=scl;scl_s2<=scl_s1;scl_s3<=scl_s2;sda_s1<=sda_in;sda_s2<=sda_s1;sda_s3<=sda_s2; end
end
wire scl_rise=~scl_s3&scl_s2, scl_fall=scl_s3&~scl_s2;
wire sda_fall=sda_s3&~sda_s2, sda_rise=~sda_s3&sda_s2;
wire start_det=scl_s2&sda_fall, stop_det=scl_s2&sda_rise;
typedef enum logic [2:0] {S_IDLE,S_ADDR,S_ACK_ADDR,S_DATA,S_ACK_DATA,S_WAIT} state_t;
state_t state; reg [3:0] bit_cnt; reg [6:0] addr_reg; reg rw_bit; reg [7:0] shift_reg;
always @(posedge clk or posedge rst) begin
    if (rst) begin state<=S_IDLE;bit_cnt<=0;addr_reg<=0;rw_bit<=0;shift_reg<=0;
        rx_data<=0;rx_valid<=0;sda_out<=0;sda_oe<=0;addr_match<=0; end
    else begin
        rx_valid<=0;
        if (stop_det) begin state<=S_IDLE;sda_oe<=0;addr_match<=0; end
        else if (start_det) begin state<=S_ADDR;bit_cnt<=0;shift_reg<=0;sda_oe<=0;addr_match<=0; end
        else begin
            case (state)
                S_IDLE: sda_oe<=0;
                S_ADDR: if (scl_rise) begin
                    shift_reg<={shift_reg[6:0],sda_s2};
                    if (bit_cnt==6) addr_reg<={shift_reg[5:0],sda_s2};
                    if (bit_cnt==7) begin rw_bit<=sda_s2;bit_cnt<=0;state<=S_ACK_ADDR; end
                    else bit_cnt<=bit_cnt+1;
                end
                S_ACK_ADDR: if (addr_reg==SLAVE_ADDR) begin
                    addr_match<=1;sda_oe<=1;
                    if (scl_fall) begin sda_oe<=0;shift_reg<=tx_data;bit_cnt<=0;state<=S_DATA; end
                end else begin addr_match<=0;sda_oe<=0;state<=S_IDLE; end
                S_DATA: if (rw_bit==0) begin
                    if (scl_rise) begin
                        shift_reg<={shift_reg[6:0],sda_s2};
                        if (bit_cnt==7) begin rx_data<={shift_reg[6:0],sda_s2};rx_valid<=1;bit_cnt<=0;state<=S_ACK_DATA; end
                        else bit_cnt<=bit_cnt+1;
                    end
                end else begin
                    if (scl_fall) begin
                        if (bit_cnt==7) begin sda_oe<=0;bit_cnt<=0; end
                        else begin shift_reg<={shift_reg[6:0],1'b0};sda_out<=shift_reg[6];bit_cnt<=bit_cnt+1; end
                    end
                    if (scl_rise&&bit_cnt==0) state<=S_WAIT;
                end
                S_ACK_DATA: begin sda_oe<=1; if (scl_fall) begin sda_oe<=0;shift_reg<=0;bit_cnt<=0;state<=S_DATA; end end
                S_WAIT: begin sda_oe<=0;state<=S_IDLE; end
                default: state<=S_IDLE;
            endcase
        end
    end
end
endmodule