// ============================================================================
// rule_classifier.v - 自动分类B/S规则的行为
// 运行N步后统计：种群变化、空间分布、周期检测
// ============================================================================
module rule_classifier #(
    parameter WIDTH  = 32,
    parameter HEIGHT = 32,
    parameter STEPS  = 256
)(
    input  wire             clk,
    input  wire             rst_n,
    input  wire [8:0]       born,
    input  wire [8:0]       survive,
    input  wire             start,
    output wire [2:0]       category,    // 0=稳定 1=振荡 2=混沌 3=复杂 4=消亡
    output wire [31:0]      period,      // 检测到的周期
    output wire             done
);

    // 实例化可变规则CA
    wire [WIDTH*HEIGHT-1:0] ca_state;
    wire [31:0] ca_gen;
    wire [31:0] ca_pop;
    wire ca_init, ca_en;

    life_variable_rule #(.WIDTH(WIDTH), .HEIGHT(HEIGHT)) ca (
        .clk(clk), .rst_n(rst_n), .enable(ca_en),
        .init(ca_init), .seed({(WIDTH*HEIGHT){1'b0}} | (1 << (WIDTH*HEIGHT/2))),
        .born(born), .survive(survive),
        .state(ca_state), .generation(ca_gen), .population(ca_pop)
    );

    // 种群历史缓冲（用于周期检测）
    reg [31:0] pop_history [0:STEPS-1];
    reg [31:0] step_cnt;
    reg        running;
    reg [2:0]  cat_reg;
    reg [31:0] per_reg;
    reg        done_reg;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            step_cnt <= 32'd0;
            running  <= 1'b0;
            cat_reg  <= 3'd0;
            per_reg  <= 32'd0;
            done_reg <= 1'b0;
        end else if (start && !running) begin
            step_cnt <= 32'd0;
            running  <= 1'b1;
            done_reg <= 1'b0;
        end else if (running) begin
            pop_history[step_cnt] <= ca_pop;

            if (step_cnt == STEPS - 1) begin
                running  <= 1'b0;
                done_reg <= 1'b1;

                // 简单分类逻辑
                if (ca_pop == 0)
                    cat_reg <= 3'd4;  // 消亡
                else if (ca_pop == pop_history[STEPS/2])
                    cat_reg <= 3'd0;  // 稳定
                else
                    cat_reg <= 3'd2;  // 其他（简化）
            end else begin
                step_cnt <= step_cnt + 32'd1;
            end
        end
    end

    assign category = cat_reg;
    assign period   = per_reg;
    assign done     = done_reg;

endmodule