// ============================================================================
// frame_buffer_dual.v - 双缓冲帧缓冲控制器
// 写端口连接CA核心，读端口连接显示控制器
// 两个Bank交替使用，消除画面撕裂
// ============================================================================
module frame_buffer_dual #(
    parameter WIDTH  = 160,
    parameter HEIGHT = 120,
    parameter DEPTH  = 4           // 每像素位深
)(
    input  wire              clk,
    input  wire              rst_n,
    // 写接口（CA核心）
    input  wire [7:0]        wr_x,
    input  wire [7:0]        wr_y,
    input  wire [DEPTH-1:0]  wr_data,
    input  wire              wr_en,
    input  wire              frame_swap,
    // 读接口（显示控制器）
    input  wire [7:0]        rd_x,
    input  wire [7:0]        rd_y,
    output wire [DEPTH-1:0]  rd_data,
    output wire              wr_bank
);

    localparam TOTAL = WIDTH * HEIGHT;
    localparam ADDR_W = $clog2(TOTAL);

    reg [DEPTH-1:0] bank_a [0:TOTAL-1];
    reg [DEPTH-1:0] bank_b [0:TOTAL-1];
    reg write_sel;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            write_sel <= 1'b0;
        else if (frame_swap)
            write_sel <= ~write_sel;
    end

    wire [ADDR_W-1:0] wr_addr = wr_y * WIDTH + wr_x;
    wire [ADDR_W-1:0] rd_addr = rd_y * WIDTH + rd_x;

    always @(posedge clk) begin
        if (wr_en) begin
            if (write_sel) bank_b[wr_addr] <= wr_data;
            else           bank_a[wr_addr] <= wr_data;
        end
    end

    assign rd_data = write_sel ? bank_a[rd_addr] : bank_b[rd_addr];
    assign wr_bank = write_sel;

endmodule