// ============================================================================
// ca_rule90_opt.v - 规则90的优化硬件实现
// 规则90等价于 XOR(left, right)，无需查找表
// ============================================================================
module ca_rule90_opt #(
    parameter WIDTH = 128              // 支持更大宽度，因为逻辑极简
)(
    input  wire             clk,
    input  wire             rst_n,
    input  wire             enable,
    input  wire             init,
    input  wire [WIDTH-1:0] seed,
    output wire [WIDTH-1:0] state
);

    reg [WIDTH-1:0] curr_state;
    wire [WIDTH-1:0] next_state;

    // 规则90: next[i] = curr[i-1] XOR curr[i+1]
    // 环形边界
    assign next_state[0]        = curr_state[WIDTH-1] ^ curr_state[1];
    assign next_state[WIDTH-1]  = curr_state[WIDTH-2] ^ curr_state[0];

    genvar i;
    generate
        for (i = 1; i < WIDTH-1; i = i + 1) begin : gen_xor
            assign next_state[i] = curr_state[i-1] ^ curr_state[i+1];
        end
    endgenerate

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            curr_state <= {WIDTH{1'b0}};
        else if (init)
            curr_state <= seed;
        else if (enable)
            curr_state <= next_state;
    end

    assign state = curr_state;

endmodule